In general, CMOS image sensors are fabricated in a MOS manufacturing process. Thus, unlike CCD image sensors, pixel arrays and AD converter circuits can be mounted on the same chip.
Three on-chip structures are known about AD converter circuits, as described below.
FIG. 6 is a schematic view illustrating a typical structure of a CMOS image sensor including such on-chip AD converter circuits. In FIG. 6, shaded blocks 200A, 200B, and 200C show three typical layouts of AD converter circuits. However, in practice, one of these layouts is adopted.
The structure of a known CMOS image sensor will now be described with reference to FIG. 6.
As shown in the drawing, this CMOS image sensor includes a pixel array 210, a vertical (V) selection circuit 220, column-signal processing units 230, a horizontal (H) selection circuit 240, and an output unit 250 on one chip.
The pixel array 210 includes many pixels in a two-dimensional array (a matrix).
The V selection circuit 220 sequentially selects the pixels in the pixel array 210 row by row in the vertical direction (the direction along columns) to drive the selected pixels.
The column-signal processing units 230 correspond to respective columns of the pixels in the pixel array 210 and sequentially receive signals from the individual pixels 211 to, for example, remove fixed-pattern noise and adjust gain.
The H selection circuit 240 sequentially selects the column-signal processing units 230 in the direction along rows to output the individual pixel signals processed in the column-signal processing units 230 to an output line 241.
The output unit 250 receives the pixel signals from the output line 241 and finally processes these signals to output the processed signals as image signals.
In such a CMOS image sensor, the following three types of structures including on-chip AD converter circuits are possible.
The shaded blocks 200A in FIG. 6 show a typical layout disclosed in, for example, U.S. Pat. No. 5,461,425. In this layout, one AD converter circuit is provided for each pixel 211 to carry out AD conversion for each pixel and to output a digitized pixel signal from the pixel 211 (hereinafter, referred to as pixel-level AD conversion).
The shaded blocks 200B in FIG. 6 show another typical layout disclosed in, for example, Japanese Patent No. 253234. In this layout, one AD converter circuit is provided for each of the column-signal processing units 230 to carry out AD conversion for each column and to output a digitized pixel signal from the column-signal processing unit 230 (hereinafter, referred to as column-level AD conversion).
The shaded blocks 200C in FIG. 6 show another typical layout. In this layout, one AD converter circuit is provided for the output unit 250 to carry out sequential AD conversion on the signals from the output line 241 and to output a digitized pixel signal from the output unit 250 to the exterior of the chip (hereinafter, referred to as chip-level AD conversion). This layout is equivalent to that of an AD converter circuit connected to a device outputting analog signals.
The three types of AD conversion described above have the following problems.
(1) The pixel-level AD conversion can be simultaneously carried out for all the pixels, thereby enabling high-speed processing. However, since one AD converter circuit is provided in each pixel, the size of the pixel is increased. As a result, the area of the pixel array and the size of an optical system are disadvantageously increased. On the other hand, the aperture ratio (the area ratio of a photodiode to a pixel) is decreased, so that the sensitivity is disadvantageously decreased.
(2) The pixels used in the column-level AD conversion have a simpler structure than those in the pixel-level AD conversion. Thus, the size of the pixels can be reduced. However, when one image frame is output, AD conversion must be carried out as many times as the number of rows (for example, several hundred to several thousand times), and thus the speed of the column-level AD conversion is disadvantageously low.
Moreover, since this AD conversion is carried out in a short time, the bandwidth of the circuit needs to be increased. Thus, the noise becomes large.
Moreover, since AD conversion of one frame is sequentially carried out row by row, the difference between the timing of AD conversion of the first row and that of the last row is one frame period. Thus, this AD conversion is not suitable when time shifting in a screen needs to be minimized (for example, when an image of an object that moves quickly is captured).
(3) The characteristics of the chip-level AD conversion are the same as those of the column-level AD conversion. That is, the pixels have a simple structure. However, when one image frame is output, AD conversion must be carried out as many times as the number of pixels (for example, several hundreds of thousand to several million times), and thus the speed of the chip-level AD conversion is even lower than that of the column-level AD conversion.
Moreover, since this AD conversion is carried out in a short time, the bandwidth of the circuit needs to be increased. Thus, the noise is even larger than that in the column-level AD conversion. Moreover, since AD conversion of pixel signals for one frame is sequentially carried out pixel by pixel, the difference between the timing of AD conversion of the first pixel and that of the last pixel is one frame period. Thus, this AD conversion is not suitable when time shifting in a screen needs to be minimized.
It is an object of the present invention to provide a solid-state imaging apparatus that can rapidly carry out AD conversion with a low load and that can output high-quality digital image signals by simultaneous AD conversion, without increasing the sizes of a pixel array and an optical system.